1. Field of the Invention
The present invention relates to a data copy method for copying data to a non-volatile memory and an application processor for the data copy method.
2. Description of the Related Art
Generally, a flash memory device is a type of non-volatile memory device that is capable of maintaining stored data in the event power of the flash memory device is discontinued, and is a type of electrically erasable programmable read-only memory (EEPROM).
The flash memory device is widely used for storing a boot code in terminals, and for secondary storage in mobile systems.
The flash memory device may be classified as either a NOR-type flash memory device or a NAND-type flash memory device.
The NOR-type flash memory device uses an interfacing method of a static random access memory (SRAM) or a read-only memory (ROM).
Thus, it is straightforward to implement a circuit configuration with a processor, and it is possible to perform a high-speed data process. However, there are high manufacturing costs.
Compared with the NOR-type flash memory device, the NAND-type flash memory device has a more complex interfacing method than that of the NOR-type flash memory device.
However, the NAND-type flash memory device has relatively higher integration and relatively lower manufacturing costs.
Therefore, the NAND-type flash memory device is widely used for a memory card of a camcorder, a digital camera or an MP3 player. Additionally, the capacity of the NAND-type flash memory device has been upgraded to about 1 gigabyte (GB) from a more conventional 64 megabyte (MB) capacity.
The speed indicating how quickly data is read from or written to the NAND-type flash memory device determines the performance of an entire system.
Accordingly, the speed indicating how quickly data stored in the NAND-type flash memory device are copied to a volatile memory, such as a synchronous dynamic random access memory (SDRAM) device, is an important factor for improving the performance of an entire system.
In a conventional data copy method, such as a polling method, to copy data stored in the NAND-type flash memory device into the SDRAM, a command signal for reading the data stored in the NAND-type flash memory device is applied, then data stored in the NAND-type flash memory device are stored in a data register of a processor in response to the command signal.
The data stored in the data register are repeatedly stored in a corresponding address space of the SDRAM. The data stored in the NAND-type flash memory device are transferred by page units.
However, in the polling method, after the data stored in the NAND-type flash memory device are stored in the data register, the data stored in the data register are transferred to the SDRAM, which is repeatedly performed until all of the data stored in the NAND-type flash memory device are copied to the SDRAM. As a result, the data processing speed may be decreased.
To increase the processing speed, a direct memory access (DMA) technique is employed.
FIG. 1 is a block diagram illustrating a conventional data copy method that copies data stored in a NAND flash memory to a synchronous dynamic random access memory.
Referring to FIG. 1, when a processor 20 applies a command signal to a NAND-type flash memory device 10, data stored in the NAND-type flash memory device 10 are stored in a data register (not shown) included in the processor 20 by pages. Then, the data stored in the data register are transferred to an SDRAM 30 by performing a DMA operation.
That is, the data transferred from the NAND-type flash memory device 10 is stored in the data register included in the processor 20, so that the data may then be transferred to the SDRAM 30.
However, the time for the data to be transmitted from the NAND-type flash memory device 10 to the data register included in the processor 20 takes a longer time than that of the DMA operation, through which the data is then transferred to the SDRAM 30.
As a result, the speed benefits obtained from the DMA operation may be lost, and the efficiency of a memory bus may be degraded.
That is, there occurs a data processing time delay between the NAND-type flash memory device to the data register included in the processor 20 and the data register to the SDRAM.
The DMA operation is idle from after the data corresponding to one page are transferred to the SDRAM 30 using the DMA operation until the data corresponding to the next page are stored in the data register, and from after the storing process from the NAND-type flash memory device to the data register until the DMA operation is performed again. Thus, the speed benefit obtained from the DMA operation is lost.
Further, due to the idle time of the DMA operation, unnecessary occupancy time on the memory bus may be increased, thereby degrading the efficiency of the memory bus.